sample-and-hold circuit
英 [ˈsɑːmpl ənd həʊld ˈsɜːkɪt]
美 [ˈsæmpl ənd hoʊld ˈsɜːrkɪt]
网络 采样保持电路; 取样保持电路
双语例句
- A sample-and-hold ( S/ H) circuit as the key part of the analog-to-digital ( A/ D) converter always attracts the researcher and designer of A/ D converter.
采样保持电路作为流水线模数转换器中的重要单元一直是高速高分辨率模数转换器研究设计者十分关注的内容。 - A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.
设计了一个用于流水线型模数转换器的低压采样保持电路。 - Design and Implementation of a High-speed High-resolution Sample-and-hold Circuit
一种高速高精度采样/保持电路的设计与实现 - Study of Sample-and-hold Circuit Based on Pipeline ADC
基于流水线ADC的采样保持电路的研究 - Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
采样速度和保持精度，是采样保持电路设计制作者最为关注的两项指标。 - Low-Voltage Low-Power CMOS Sample-and-Hold Circuit
低电压低功耗CMOS采样保持电路 - Design of a High-Precision Sample-and-Hold Circuit
高精度的采样保持电路的设计 - A 10-b 80 MS/ s low power sample-and-hold circuit based on switched-capacitor ( SC) circuits was designed, which is intended for use in a 10-b 80 MS/ s pipelined A/ D converter.
给出了一种基于开关电容（SC）电路的10位80MHz采样频率低功耗采样保持电路。它是为一个10位80MS/s流水线结构A/D转换器的前端采样模块设计的。 - A New High-Speed and High-Resolution Sample-and-Hold Circuit
一种新型高速高分辨率采样保持电路 - Analysis and Design of Fully Differential Gain-boosted OPAMP Dedicated to 14 bit Sample-and-Hold Circuit
一个用于14位采样保持电路的全差分增益增强放大器的分析和设计 - Design of a High-Speed Flip-Around Sample-and-Hold Circuit
Flip-around结构高速采样保持电路的设计 - A 40 MSPS Pipelined Sample-and-Hold Circuit
一种流水型40MSPS高速采样保持器 - An Undersampling High-Resolution Low-Power Sample-and-Hold Circuit
一种欠采样应用的高精度低功耗采样/保持电路 - The filter based on ployphase interpolation principle, consists of a parallel data input, a 8 × interpolator, a 16 × sample-and-hold circuit, to over-sample ( 128 ×) the audio signal ( PCM code).
该滤波器采用多相插值原理，硬件电路包括并行数据输入接口、8倍插值器、16倍采样保持电路，实现对输入音频信号（PCM码）的128倍过采样。 - A sample-and-hold ( S/ H) circuit for 10-bit 100 MS/ s pipelined A/ D converters is presented.
设计了一个用于10位100MHz采样频率的流水线A/D转换器的采样保持电路。 - An IC electronic circuit is used to analogize the behavior of Josephson junction. A novel method based on a sample-and-hold circuit to generate the sin θ supercurrent is designed.
作者使用了由集成块所组成的电子线路来模拟Josephson结的性质，其特点是设计了一种新型的采样保存电路来模拟与sinθ成正比的超导电流。 - It is useful to solve the conflict between speed and DC gain of an amplifier in high-speed and high-resolution sample-and-hold circuit to use a speed compensation circuit.
采用速度补偿解决了高速高分辨采样保持电路对放大器要求增益高和速度快之间的矛盾。 - As an important unit of Pipelined Analog-to-Digital Converter, Sample-and-Hold circuit is always given more attention by RD whose major is high speed and high resolution pipelined ADC.
采样保持（S/H）电路单元作为高速高分辨率流水线型模数转换器中的重要单元一直是研究者十分关注的重要内容。 - The key circuit design includes a sample-and-hold gain circuit using switched-capacitor to sample or hold the signal and a preamplifier-latch comparator using two-phase clock.
在电路设计中主要包括开关电容采样的全差分运放组成的采保增益电路和两相时钟控制的带预放大器的锁存比较器。 - This thesis directs another way, using the high-speed sub-picosecond, high-precision ADC and "Sample-and-hold" circuit, which are already mature products and technologies, to measure the clock parameters.
本文另辟蹊径，利用亚皮秒的高速、高精度的ADC采样-保持电路这一成熟的产品和技术来测量时钟参数。 - The front-end sample-and-hold circuit uses double-sample technique. Bootstrapped sampling switch is applied and achieves remarkable progress on the resolution and linearity of the system.
电路最前端的采样保持电路应用双采样技术，结合栅压自举采样开关，大幅提高了电路的精度和线性度。 - The optimization of sample-and-hold circuit relieves the high-speed sampling clock feedthrough and charge injection effect.
前端采样保持电路的优化有效缓解了高速采样下的时钟馈通和电荷注入效应，缓冲级巧妙地将衬底电容与输出隔开，提高了电路的线性度。